Master’s Thesis

Mixed-Signal Design of an All-Digital PLL in a Leading-Edge CMOS Process

Ref. 2026_005

Phase-locked loop (PLL) circuits are essential building blocks for the frequency generation in both wireline and wireless communication systems. Key performance requirements include spectral purity, low power consumption, and minimal silicon area.

In this project, an all-digital PLL (ADPLL) will be implemented using a state of the art CMOS process. ADPLLs employ a digitally controlled oscillator (DCO) and a synthesized loop filter to achieve a compact layout. Unlike PLLs that use analog loop filters, ADPLLs require a mixed-signal simulation flow that integrates VHDL netlists with analog transistor- level models.

The objective of this work is to develop and apply a mixed-signal design methodology to realize an ADPLL capable of generating frequencies around 20 GHz while meeting the spectral purity requirements of PCIe I/Os. This project offers the opportunity to explore new concepts and design strategies for ADPLLs within an industrial research environment.

Applicants should have completed coursework in digital IC design and/or analog integrated circuits. The project is intended primarily for a Master’s thesis, though in exceptional cases it may be suitable for a Bachelor’s thesis. Please note that paid internships are not available for this project.





Diversity & Work Environment

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