Staefa, Switzerland

Practical Trainee

Stäfa, Switzerland | On site

6‑month full-time internship

Start date: ASAP

Research & Development delivers hearing solutions and services for hearing impaired people, hearing care professionals, and further related people, in the form of hearing devices, accessories, web services, mobile applications, and PC software.

Your tasks

• Define with stakeholders the requirements for an Ethernet interface on an Artix UltraScale+ FPGA
• Evaluate and select suitable open-source Ethernet IP cores or external controller solutions based on technical requirements, performance, and integration constraints
• Design and implement an Ethernet controller on an Artix UltraScale+ FPGA
• Integration of the Ethernet controller into existing SoC design (uBlaze + AXI bus) including necessary extension to uBlaze firmwareDevelop testbenches including regression tests for the designed Ethernet block, ensuring functional correctness and protocol compliance
• Verify, debug, and bring up the design on the FPGA board and associated hardware environment
• Develop PC driver and software for integration and testing
• Create and maintain documentation

Your profile

• Microelectronics student
• Experience with FPGA design
• Experience with Verilog and/or VHDL
• Knowledge of digital design verification
• Knowledge of Python programming for testing and integration
• Basic C programming Skills

Our offer

We can offer you a new challenge, with interesting tasks and much more – including an open corporate culture, flat hierarchies, support for further training and development, opportunities to take on responsibility, an excellent range of foods, sports and cultural facilities, attractive employment conditions, and flexible working time models in various roles. #LI-NB1